FIG. 1 is a schematic block diagram of a portion of a conventional memory-cell array 100 for a dynamic random access memory (DRAM). The memory-cell array 100 includes a number of memory cells 102 arranged in rows and columns, each memory cell including an access switch in the form of an NMOS access transistor 104 and a storage element in the form of a capacitor 106. The capacitor 106 includes a first plate that receives a reference potential which is typically equal to approximately a supply voltage Vdd divided by two (Vdd/2), with the first plate typically being common to the first plates of all other capacitors in the array 100. A second plate of the capacitor 106 is connected to the source of the transistor 104. Each of the memory cells 102 stores a single bit of binary data in the form of a charge stored on and thus a voltage across the capacitor 106. A voltage of approximately Vdd at the second plate of the capacitor 106 corresponds to a first binary data value and a voltage of approximately zero volts at the second plate corresponds to a second binary data value.
The memory cells 102 are arranged in n rows and m columns, with one memory cell positioned at the intersection of each row and column. Each row of memory cells 102 has an associated word line WL0-WLN-1 and each column of memory cells has an associated pair of true and complementary bit lines BL0, BL0*-BLM-1, BLM-1*, where the “*” indicates that data on the complementary bit line is the complement of data on the associated true bit line, as will be appreciated by those skilled in the art. The bit lines may be referred to generally as BL, BL* and the word lines as WL in the following description. Each memory cell 102 in a given row of memory cells has a control terminal in the form of the gate of the transistor 104 connected to the associated word line WL0-WLN-1 and each memory cell in a given column of memory cells has a data terminal in the form of a drain terminal of the transistor 104 connected to one of the associated complementary bit lines BL0, BL0*-BLM-1, BLM-1*.
Each pair of bit lines BL,BL* is connected to a corresponding sense amplifier 108 that senses and stores data in an addressed memory cell 102 connected to one of the corresponding bit lines. In the simplified diagram of FIG. 1, each sense amplifier is assumed to include isolation transistors for selectively coupling and decoupling the sense amplifier from the corresponding bit lines BL, BL* and equilibration transistors connected between the pair of bit lines for driving or “equilibrating” the bit lines to equal voltages when activated.
In operation of the memory-cell array 100, before data is read from the memory cells 102, control circuitry (not shown) in the DRAM executes an equilibration cycle. During the equilibration cycle, row drivers in the control circuitry drive each of the word lines WL low, turning OFF each access transistor 104 and thereby deselecting each of the memory cells 102. At the same time, each sense amplifier 108 equilibrates the associated bit lines BL, BL* to equalize the voltage on each bit line to approximately Vdd/2. After the equilibration cycle, the row driver of the word line WL corresponding to the addressed memory cells 102 is initially driven with the supply voltage Vdd. In response to the voltage Vdd on the activated word line WL, the access transistors 104 in each memory cell 102 connected to that word line are turned ON and charge is transferred between each capacitor 106 and the associated bit line BL, BL*. For example, if the word line WL0 is activated charge is transferred between the capacitors 106 in each memory cell 102 connected to this word line and the associated complementary bit lines BL0*-BLM-1*.
This charge transfer results in the voltages on each of the complementary bit lines BL0*-BLM-1* either increasing slightly above or decreasing slightly below the equilibrated voltage of Vdd/2, depending on the logic state of data stored in the corresponding memory cell 102. Each sense amplifier 108 then compares the voltage on the complementary bit line BL, BL* connected to the activated memory cell 102 to the voltage of Vdd/2 on the other bit line. In response to the sensed voltage differential between each pair of bit complementary lines BL and BL*, each sense amplifier 108 drives the higher bit line to approximately Vdd and drives the lower bit line to approximately zero volts. The voltage levels on each pair of bit lines BL, BL* now represents the binary value of the data stored in the activated memory cell 102 in that column of memory cells. The data contents of the addressed memory cells 102 are then read from each sense amplifier 108 connected to a column of an addressed memory cell by read/write circuitry (not shown in FIG. 1).
To sense the data stored in each memory cell 102 during a read operation, the row drivers drive each word line WL to the supply voltage Vdd as just described. Because this operation results in charge being transferred from the capacitor 106 in each activated memory cell 102 to the corresponding bit line BL, BL*, the charge stored in the capacitors must be restored to its initial value so that the data initially stored in each memory cell is not destroyed by the read operation. Accordingly, after the data stored in the addressed memory cells has been sensed, the row drivers drive each word line WL with a pumped voltage Vpp that is greater than the supply voltage Vdd. This enables the storage capacitors 106 to be charged to the full supply voltage Vdd when binary data corresponding to this voltage level is to be stored in the memory cell 102. More specifically, to enable the access transistors 104 in each memory cell 102 to charge the capacitor 106 to the full voltage Vdd on the associated bit line BL, BL* the voltage on the word line WL applied to the gate of that transistor must be greater than the voltage Vdd. This is true because to remain turned ON, each transistor 104 must have a gate-to-source voltage that is greater than a threshold voltage VT required to keep the transistor turned ON. This threshold voltage VT is shown for the memory cell 102 in row 0 and column 0 in the array 100 and corresponds to the voltage between the capacitor 106 and the word line WL0 as shown in FIG. 1. Thus, to remain turned ON to charge the capacitor 106 to the full supply voltage Vdd, the pumped voltage Vpp on the word line WL0 must be greater than the supply voltage Vdd by at least the threshold voltage VT (Vpp>Vdd+VT). Note that many in many conventional arrays 100 the word lines WL are simply either held low to deselect the corresponding memory cells or are driven to the pumped supply voltage Vpp to sense and restore data stored in the cells, without the intervening application of the supply voltage Vdd.
The operation of the array 100 during a write operation is similar. Write data is transferred through a read/write data path (not shown) and applied to the respective bit lines BL, BL* of addressed memory cells 102, driving the voltages on pairs of bit lines to complementary voltage levels corresponding to the write data. Thus, for each pair of bit lines BL, BL*, one bit line is driven to Vdd and one is driven to zero volts. To apply the full voltage Vdd to the storage capacitor 106 in an addressed memory cell 102 when required, the word line WL of the row containing the addressed memory cell must be driven to pumped voltage Vpp as previously described. This allows the full values of the voltages on the bit lines BL, BL* corresponding to the write data to be applied through the access transistors 104 to the capacitors 106 in each addressed memory cell 102 and thereby store charge in each capacitor corresponding to a bit of the write data.
The pumped voltage Vpp required for proper operation of the DRAM array 100 may be generated in variety of different ways. A charge pump (not shown) in the DRAM containing the memory-cell array 100 typically generates the pumped voltage Vpp from the supply voltage Vdd, as will be appreciated by those skilled in the art. Alternatively, in some situations the pumped voltage Vpp may be available as a separately provided external supply voltage that may then simply be applied to the array 100 as required. For example, availability of dual power supplies, namely Vdd and Vpp, is common in many application specific integrated circuits (ASICs) where the low supply voltage Vdd powers the memory-cell array 100 and associated peripheral and logic circuitry while the pumped supply voltage Vpp powers other circuitry such as bipolar components. In this situation, the pumped voltage Vpp being generated for the bipolar components may be applied to the array 100 without the need for a charge pump or other voltage increasing circuit if Vpp>Vdd+VT as previously described. If the available voltage Vpp is not greater than Vdd+VT, then a charge pump, boost circuit, or some other suitable circuit is used to increase the voltage Vpp to the required level. A charge pump is a circuit that continuously provides an increased voltage Vpp while a boost circuit utilizes capacitors to provide the increased voltage Vpp only when needed, as will be understood by those skilled in the art.
In the situation where the supply voltages Vdd and Vpp are provided by independent external supply voltages, situations can arise where the pumped voltage Vpp has a value that is higher than required for proper operation of the DRAM array 100. This can occur whether the externally supplied voltage Vpp is applied directly or where the voltage Vpp is increased through a charge pump or boost circuit to the required level. An example of such a situation is where the supply voltage Vpp has a maximum value with a permissible operating range and the supply voltage Vdd has a minimum value with a permissible operating range. For example, assume nominal values for the voltages Vpp and Vdd are 4.2 volts and 3.3 volts, respectively, and that the tolerance or permissible operating range of each is plus or minus 10%. In this situation, assuming a threshold voltage VT of 0.7 volts for the access transistors 104 in the array 100, then Vpp>Vdd+VT (4.2v>3.3v+0.7v) so no increase in the voltage Vpp is required. Now assume the pumped supply voltage Vpp is at its minimum permissible value of 3.78 volts (4.2v−0.42v) and the supply voltage Vdd is at its maximum permissible value of 3.63v (3.3v+0.33v). In this situation, the pumped supply voltage Vpp is no longer greater than the supply voltage Vdd by the required amount, namely 3.78v is not greater than 3.63v+0.7v=4.33v. The pumped voltage Vpp needs to be increased to ensure proper operation in this situation. This example illustrates why the supply voltage Vpp is typically increased through a charge pump or boost circuit to ensure that Vpp always has a magnitude great enough to ensure proper operation.
These examples illustrate that as the independent supply voltages Vpp and Vdd vary over time or with changes in temperature, situations can occur where sometimes increasing the pumped voltage Vpp is necessary while in other situations it is not. As a result, conventional ASICs increase the pumped voltage Vpp, typically through a charge pump or boost circuit, above some minimum required to ensure that the pumped voltage always has a sufficient value to ensure proper operation of the DRAM portion of the ASIC. This ensures proper operation of the DRAM portion of the ASIC but places stresses on components in the array 100 and other components in the DRAM portion when the voltage Vpp is increased even though not required for proper operation. The first example above illustrates a situation where increasing is not required for proper operation, namely where the pumped supply voltage Vpp equals 4.2 volts and the supply voltage Vdd equals 3.3 volts. In this situation, no increase in the voltage Vpp is required. With the conventional approach, however, the pumped voltage Vpp of 4.2 volts is nonetheless increased to a higher value, such as 5 volts for example. This results in 5 volts being applied on each activated word line WL and 3.3 volts being applied on the bit lines BL, BL*. As a result, the gate-to-source voltage of the access transistors 104 is 1.7 volts or about 1 volt greater than the required 0.7 volts. Moreover, when a logic zero is being stored in a memory cell 102 the gate-to-source voltage for the corresponding access transistor 104 is 5 volts (i.e., 5 volts on the word line WL and zero volts on the source and drain).
Higher voltages across components in the memory-cell array 100 such as the NMOS transistors 104 stress these components and can thereby damage and reduce the operable life of such components, which reduces the operational life of the ASIC containing the DRAM. This is true, for example, because higher voltages break down oxide layers in such components, such as the oxide layer formed between the gate and a channel region of each access transistor 104.
There is a need for a circuit and method of providing increased voltages in DRAMs and other integrated circuit devices that are great enough to ensure proper operation of the devices but not too large so as to reduce the operational lives of such devices.